#ifndef	__SIM_H__
#define	__SIM_H__

//
///* ----------------------------------------------------------------------------
//   -- SIM
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SIM_Peripheral SIM
// * @{
// */
//
///** SIM - Peripheral register structure */
////typedef struct SIM_MemMap {
////  unsigned long SOPT1;                                  /**< System Options Register 1, offset: 0x0 */
////  unsigned char RESERVED_0[4096];
////  unsigned long SOPT2;                                  /**< System Options Register 2, offset: 0x1004 */
////  unsigned char RESERVED_1[4];
////  unsigned long SOPT4;                                  /**< System Options Register 4, offset: 0x100C */
////  unsigned long SOPT5;                                  /**< System Options Register 5, offset: 0x1010 */
////  unsigned long SOPT6;                                  /**< System Options Register 6, offset: 0x1014 */
////  unsigned long SOPT7;                                  /**< System Options Register 7, offset: 0x1018 */
////  unsigned char RESERVED_2[8];
////  unsigned long SDID;                                   /**< System Device Identification Register, offset: 0x1024 */
////  unsigned long SCGC1;                                  /**< System Clock Gating Control Register 1, offset: 0x1028 */
////  unsigned long SCGC2;                                  /**< System Clock Gating Control Register 2, offset: 0x102C */
////  unsigned long SCGC3;                                  /**< System Clock Gating Control Register 3, offset: 0x1030 */
////  unsigned long SCGC4;                                  /**< System Clock Gating Control Register 4, offset: 0x1034 */
////  unsigned long SCGC5;                                  /**< System Clock Gating Control Register 5, offset: 0x1038 */
////  unsigned long SCGC6;                                  /**< System Clock Gating Control Register 6, offset: 0x103C */
////  unsigned long SCGC7;                                  /**< System Clock Gating Control Register 7, offset: 0x1040 */
////  unsigned long CLKDIV1;                                /**< System Clock Divider Register 1, offset: 0x1044 */
////  unsigned long CLKDIV2;                                /**< System Clock Divider Register 2, offset: 0x1048 */
////  unsigned long FCFG1;                                  /**< Flash Configuration Register 1, offset: 0x104C */
////  unsigned long FCFG2;                                  /**< Flash Configuration Register 2, offset: 0x1050 */
////  unsigned long UIDH;                                   /**< Unique Identification Register High, offset: 0x1054 */
////  unsigned long UIDMH;                                  /**< Unique Identification Register Mid-High, offset: 0x1058 */
////  unsigned long UIDML;                                  /**< Unique Identification Register Mid Low, offset: 0x105C */
////  unsigned long UIDL;                                   /**< Unique Identification Register Low, offset: 0x1060 */
////} volatile *SIM_MemMapPtr;
//
///* ----------------------------------------------------------------------------
//   -- SIM - Register accessor macros
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
// * @{
// */
//
//
///* SIM - Register accessors */
//#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
//#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
//#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
//#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
//#define SIM_SOPT6_REG(base)                      ((base)->SOPT6)
//#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
//#define SIM_SDID_REG(base)                       ((base)->SDID)
//#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
//#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
//#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
//#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
//#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
//#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
//#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
//#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
//#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
//#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
//#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
//#define SIM_UIDH_REG(base)                       ((base)->UIDH)
//#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
//#define SIM_UIDML_REG(base)                      ((base)->UIDML)
//#define SIM_UIDL_REG(base)                       ((base)->UIDL)
//
///**
// * @}
// */ /* end of group SIM_Register_Accessor_Macros */
//
//
///* ----------------------------------------------------------------------------
//   -- SIM Register Masks
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SIM_Register_Masks SIM Register Masks
// * @{
// */
//
///* SOPT1 Bit Fields */
//#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
//#define SIM_SOPT1_RAMSIZE_SHIFT                  12
////#define SIM_SOPT1_RAMSIZE(x)                     (((unsigned long)(((unsigned long)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
//#define SIM_SOPT1_OSC32KSEL_MASK                 0x80000u
//#define SIM_SOPT1_OSC32KSEL_SHIFT                19
//#define SIM_SOPT1_MS_MASK                        0x800000u
//#define SIM_SOPT1_MS_SHIFT                       23
///* SOPT2 Bit Fields */
//#define SIM_SOPT2_MCGCLKSEL_MASK                 0x1u
//#define SIM_SOPT2_MCGCLKSEL_SHIFT                0
//#define SIM_SOPT2_FBSL_MASK                      0x300u
//#define SIM_SOPT2_FBSL_SHIFT                     8
////#define SIM_SOPT2_FBSL(x)                        (((unsigned long)(((unsigned long)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
//#define SIM_SOPT2_CMTUARTPAD_MASK                0x800u
//#define SIM_SOPT2_CMTUARTPAD_SHIFT               11
//#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
//#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
//#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
//#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
//#define SIM_SOPT2_I2SSRC_MASK                    0x3000000u
//#define SIM_SOPT2_I2SSRC_SHIFT                   24
////#define SIM_SOPT2_I2SSRC(x)                      (((unsigned long)(((unsigned long)(x))<<SIM_SOPT2_I2SSRC_SHIFT))&SIM_SOPT2_I2SSRC_MASK)
//#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
//#define SIM_SOPT2_SDHCSRC_SHIFT                  28
////#define SIM_SOPT2_SDHCSRC(x)                     (((unsigned long)(((unsigned long)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
///* SOPT4 Bit Fields */
//#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
//#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
//#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
//#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
//#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
//#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
//#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
//#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
//#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
//#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
//#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
//#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
////#define SIM_SOPT4_FTM1CH0SRC(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
//#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
//#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
//#define SIM_SOPT4_FTM2CH0SRC(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
//#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
//#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
//#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
//#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
//#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
//#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
///* SOPT5 Bit Fields */
//#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
//#define SIM_SOPT5_UART0TXSRC_SHIFT               0
//#define SIM_SOPT5_UART0TXSRC(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
//#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
//#define SIM_SOPT5_UART0RXSRC_SHIFT               2
//#define SIM_SOPT5_UART0RXSRC(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
//#define SIM_SOPT5_UARTTXSRC_MASK                 0x30u
//#define SIM_SOPT5_UARTTXSRC_SHIFT                4
//#define SIM_SOPT5_UARTTXSRC(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_SOPT5_UARTTXSRC_SHIFT))&SIM_SOPT5_UARTTXSRC_MASK)
//#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
//#define SIM_SOPT5_UART1RXSRC_SHIFT               6
//#define SIM_SOPT5_UART1RXSRC(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
///* SOPT6 Bit Fields */
//#define SIM_SOPT6_RSTFLTSEL_MASK                 0x1F000000u
//#define SIM_SOPT6_RSTFLTSEL_SHIFT                24
//#define SIM_SOPT6_RSTFLTSEL(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_SOPT6_RSTFLTSEL_SHIFT))&SIM_SOPT6_RSTFLTSEL_MASK)
//#define SIM_SOPT6_RSTFLTEN_MASK                  0xE0000000u
//#define SIM_SOPT6_RSTFLTEN_SHIFT                 29
//#define SIM_SOPT6_RSTFLTEN(x)                    (((unsigned long)(((unsigned long)(x))<<SIM_SOPT6_RSTFLTEN_SHIFT))&SIM_SOPT6_RSTFLTEN_MASK)
///* SOPT7 Bit Fields */
//#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
//#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
//#define SIM_SOPT7_ADC0TRGSEL(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
//#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
//#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
//#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
//#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
//#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
//#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
//#define SIM_SOPT7_ADC1TRGSEL(x)                  (((unsigned long)(((unsigned long)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
//#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
//#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
//#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
//#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
///* SDID Bit Fields */
//#define SIM_SDID_PINID_MASK                      0xFu
//#define SIM_SDID_PINID_SHIFT                     0
//#define SIM_SDID_PINID(x)                        (((unsigned long)(((unsigned long)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
//#define SIM_SDID_FAMID_MASK                      0x70u
//#define SIM_SDID_FAMID_SHIFT                     4
//#define SIM_SDID_FAMID(x)                        (((unsigned long)(((unsigned long)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
//#define SIM_SDID_REVID_MASK                      0xF000u
//#define SIM_SDID_REVID_SHIFT                     12
//#define SIM_SDID_REVID(x)                        (((unsigned long)(((unsigned long)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
///* SCGC1 Bit Fields */
//#define SIM_SCGC1_UART4_MASK                     0x400u
//#define SIM_SCGC1_UART4_SHIFT                    10
//#define SIM_SCGC1_UART5_MASK                     0x800u
//#define SIM_SCGC1_UART5_SHIFT                    11
///* SCGC2 Bit Fields */
//#define SIM_SCGC2_DAC0_MASK                      0x1000u
//#define SIM_SCGC2_DAC0_SHIFT                     12
//#define SIM_SCGC2_DAC1_MASK                      0x2000u
//#define SIM_SCGC2_DAC1_SHIFT                     13
///* SCGC3 Bit Fields */
//#define SIM_SCGC3_FLEXCAN1_MASK                  0x10u
//#define SIM_SCGC3_FLEXCAN1_SHIFT                 4
//#define SIM_SCGC3_SPI2_MASK                      0x1000u
//#define SIM_SCGC3_SPI2_SHIFT                     12
//#define SIM_SCGC3_SDHC_MASK                      0x20000u
//#define SIM_SCGC3_SDHC_SHIFT                     17
//#define SIM_SCGC3_FTM2_MASK                      0x1000000u
//#define SIM_SCGC3_FTM2_SHIFT                     24
//#define SIM_SCGC3_ADC1_MASK                      0x8000000u
//#define SIM_SCGC3_ADC1_SHIFT                     27
///* SCGC4 Bit Fields */
//#define SIM_SCGC4_EWM_MASK                       0x2u
//#define SIM_SCGC4_EWM_SHIFT                      1
//#define SIM_SCGC4_CMT_MASK                       0x4u
//#define SIM_SCGC4_CMT_SHIFT                      2
//#define SIM_SCGC4_I2C0_MASK                      0x40u
//#define SIM_SCGC4_I2C0_SHIFT                     6
//#define SIM_SCGC4_I2C1_MASK                      0x80u
//#define SIM_SCGC4_I2C1_SHIFT                     7
//#define SIM_SCGC4_UART0_MASK                     0x400u
//#define SIM_SCGC4_UART0_SHIFT                    10
//#define SIM_SCGC4_UART1_MASK                     0x800u
//#define SIM_SCGC4_UART1_SHIFT                    11
//#define SIM_SCGC4_UART2_MASK                     0x1000u
//#define SIM_SCGC4_UART2_SHIFT                    12
//#define SIM_SCGC4_UART3_MASK                     0x2000u
//#define SIM_SCGC4_UART3_SHIFT                    13
//#define SIM_SCGC4_CMP_MASK                       0x80000u
//#define SIM_SCGC4_CMP_SHIFT                      19
//#define SIM_SCGC4_VREF_MASK                      0x100000u
//#define SIM_SCGC4_VREF_SHIFT                     20
//#define SIM_SCGC4_LLWU_MASK                      0x10000000u
//#define SIM_SCGC4_LLWU_SHIFT                     28
///* SCGC5 Bit Fields */
//#define SIM_SCGC5_LPTIMER_MASK                   0x1u
//#define SIM_SCGC5_LPTIMER_SHIFT                  0
//#define SIM_SCGC5_REGFILE_MASK                   0x2u
//#define SIM_SCGC5_REGFILE_SHIFT                  1
//#define SIM_SCGC5_TSI_MASK                       0x20u
//#define SIM_SCGC5_TSI_SHIFT                      5
//#define SIM_SCGC5_PORTA_MASK                     0x200u
//#define SIM_SCGC5_PORTA_SHIFT                    9
//#define SIM_SCGC5_PORTB_MASK                     0x400u
//#define SIM_SCGC5_PORTB_SHIFT                    10
//#define SIM_SCGC5_PORTC_MASK                     0x800u
//#define SIM_SCGC5_PORTC_SHIFT                    11
//#define SIM_SCGC5_PORTD_MASK                     0x1000u
//#define SIM_SCGC5_PORTD_SHIFT                    12
//#define SIM_SCGC5_PORTE_MASK                     0x2000u
//#define SIM_SCGC5_PORTE_SHIFT                    13
///* SCGC6 Bit Fields */
//#define SIM_SCGC6_FTFL_MASK                      0x1u
//#define SIM_SCGC6_FTFL_SHIFT                     0
//#define SIM_SCGC6_DMAMUX_MASK                    0x2u
//#define SIM_SCGC6_DMAMUX_SHIFT                   1
//#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
//#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
//#define SIM_SCGC6_DSPI0_MASK                     0x1000u
//#define SIM_SCGC6_DSPI0_SHIFT                    12
//#define SIM_SCGC6_SPI1_MASK                      0x2000u
//#define SIM_SCGC6_SPI1_SHIFT                     13
//#define SIM_SCGC6_I2S_MASK                       0x8000u
//#define SIM_SCGC6_I2S_SHIFT                      15
//#define SIM_SCGC6_CRC_MASK                       0x40000u
//#define SIM_SCGC6_CRC_SHIFT                      18
//#define SIM_SCGC6_PDB_MASK                       0x400000u
//#define SIM_SCGC6_PDB_SHIFT                      22
//#define SIM_SCGC6_PIT_MASK                       0x800000u
//#define SIM_SCGC6_PIT_SHIFT                      23
//#define SIM_SCGC6_FTM0_MASK                      0x1000000u
//#define SIM_SCGC6_FTM0_SHIFT                     24
//#define SIM_SCGC6_FTM1_MASK                      0x2000000u
//#define SIM_SCGC6_FTM1_SHIFT                     25
//#define SIM_SCGC6_ADC0_MASK                      0x8000000u
//#define SIM_SCGC6_ADC0_SHIFT                     27
//#define SIM_SCGC6_RTC_MASK                       0x20000000u
//#define SIM_SCGC6_RTC_SHIFT                      29
///* SCGC7 Bit Fields */
//#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
//#define SIM_SCGC7_FLEXBUS_SHIFT                  0
//#define SIM_SCGC7_DMA_MASK                       0x2u
//#define SIM_SCGC7_DMA_SHIFT                      1
//#define SIM_SCGC7_MPU_MASK                       0x4u
//#define SIM_SCGC7_MPU_SHIFT                      2
///* CLKDIV1 Bit Fields */
//#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
//#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
//#define SIM_CLKDIV1_OUTDIV4(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
//#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
//#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
//#define SIM_CLKDIV1_OUTDIV3(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
//#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
//#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
//#define SIM_CLKDIV1_OUTDIV2(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
//#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
//#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
//#define SIM_CLKDIV1_OUTDIV1(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
///* CLKDIV2 Bit Fields */
//#define SIM_CLKDIV2_I2SFRAC_MASK                 0xFF00u
//#define SIM_CLKDIV2_I2SFRAC_SHIFT                8
//#define SIM_CLKDIV2_I2SFRAC(x)                   (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV2_I2SFRAC_SHIFT))&SIM_CLKDIV2_I2SFRAC_MASK)
//#define SIM_CLKDIV2_I2SDIV_MASK                  0xFFF00000u
//#define SIM_CLKDIV2_I2SDIV_SHIFT                 20
//#define SIM_CLKDIV2_I2SDIV(x)                    (((unsigned long)(((unsigned long)(x))<<SIM_CLKDIV2_I2SDIV_SHIFT))&SIM_CLKDIV2_I2SDIV_MASK)
///* FCFG1 Bit Fields */
//#define SIM_FCFG1_DEPART_MASK                    0xF00u
//#define SIM_FCFG1_DEPART_SHIFT                   8
//#define SIM_FCFG1_DEPART(x)                      (((unsigned long)(((unsigned long)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
//#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
//#define SIM_FCFG1_EESIZE_SHIFT                   16
//#define SIM_FCFG1_EESIZE(x)                      (((unsigned long)(((unsigned long)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
//#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
//#define SIM_FCFG1_PFSIZE_SHIFT                   24
//#define SIM_FCFG1_PFSIZE(x)                      (((unsigned long)(((unsigned long)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
//#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
//#define SIM_FCFG1_NVMSIZE_SHIFT                  28
//#define SIM_FCFG1_NVMSIZE(x)                     (((unsigned long)(((unsigned long)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
///* FCFG2 Bit Fields */
//#define SIM_FCFG2_MAXADDR1_MASK                  0x3F0000u
//#define SIM_FCFG2_MAXADDR1_SHIFT                 16
//#define SIM_FCFG2_MAXADDR1(x)                    (((unsigned long)(((unsigned long)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
//#define SIM_FCFG2_PFLSH_MASK                     0x800000u
//#define SIM_FCFG2_PFLSH_SHIFT                    23
//#define SIM_FCFG2_MAXADDR0_MASK                  0x3F000000u
//#define SIM_FCFG2_MAXADDR0_SHIFT                 24
//#define SIM_FCFG2_MAXADDR0(x)                    (((unsigned long)(((unsigned long)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
//#define SIM_FCFG2_SWAPPFLSH_MASK                 0x80000000u
//#define SIM_FCFG2_SWAPPFLSH_SHIFT                31
///* UIDH Bit Fields */
//#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
//#define SIM_UIDH_UID_SHIFT                       0
//#define SIM_UIDH_UID(x)                          (((unsigned long)(((unsigned long)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
///* UIDMH Bit Fields */
//#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
//#define SIM_UIDMH_UID_SHIFT                      0
//#define SIM_UIDMH_UID(x)                         (((unsigned long)(((unsigned long)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
///* UIDML Bit Fields */
//#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
//#define SIM_UIDML_UID_SHIFT                      0
//#define SIM_UIDML_UID(x)                         (((unsigned long)(((unsigned long)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
///* UIDL Bit Fields */
//#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
//#define SIM_UIDL_UID_SHIFT                       0
//#define SIM_UIDL_UID(x)                          (((unsigned long)(((unsigned long)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
//
///**
// * @}
// */ /* end of group SIM_Register_Masks */
//
//
///* SIM - Peripheral instance base addresses */
///** Peripheral SIM base pointer */
//#define SIM_BASE_PTR                             ((SIM_MemMapPtr)0x40047000u)
//
///* ----------------------------------------------------------------------------
//   -- SIM - Register accessor macros
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
// * @{
// */
//
//
///* SIM - Register instance definitions */
///* SIM */
//#define SIM_SOPT1                                SIM_SOPT1_REG(SIM_BASE_PTR)
//#define SIM_SOPT2                                SIM_SOPT2_REG(SIM_BASE_PTR)
//#define SIM_SOPT4                                SIM_SOPT4_REG(SIM_BASE_PTR)
//#define SIM_SOPT5                                SIM_SOPT5_REG(SIM_BASE_PTR)
//#define SIM_SOPT6                                SIM_SOPT6_REG(SIM_BASE_PTR)
//#define SIM_SOPT7                                SIM_SOPT7_REG(SIM_BASE_PTR)
//#define SIM_SDID                                 SIM_SDID_REG(SIM_BASE_PTR)
//#define SIM_SCGC1                                SIM_SCGC1_REG(SIM_BASE_PTR)
//#define SIM_SCGC2                                SIM_SCGC2_REG(SIM_BASE_PTR)
//#define SIM_SCGC3                                SIM_SCGC3_REG(SIM_BASE_PTR)
//#define SIM_SCGC4                                SIM_SCGC4_REG(SIM_BASE_PTR)
//#define SIM_SCGC5                                SIM_SCGC5_REG(SIM_BASE_PTR)
//#define SIM_SCGC6                                SIM_SCGC6_REG(SIM_BASE_PTR)
//#define SIM_SCGC7                                SIM_SCGC7_REG(SIM_BASE_PTR)
//#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM_BASE_PTR)
//#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM_BASE_PTR)
//#define SIM_FCFG1                                SIM_FCFG1_REG(SIM_BASE_PTR)
//#define SIM_FCFG2                                SIM_FCFG2_REG(SIM_BASE_PTR)
//#define SIM_UIDH                                 SIM_UIDH_REG(SIM_BASE_PTR)
//#define SIM_UIDMH                                SIM_UIDMH_REG(SIM_BASE_PTR)
//#define SIM_UIDML                                SIM_UIDML_REG(SIM_BASE_PTR)
//#define SIM_UIDL                                 SIM_UIDL_REG(SIM_BASE_PTR)
//
///**
// * @}
// */ /* end of group SIM_Register_Accessor_Macros */
//
//
///**
// * @}
// */ /* end of group SIM_Peripheral */


//******************************************************************************
//
// The following are defines for the base address of the SIM_BASE
//
//******************************************************************************
#define	SIM_BASE				0x40047000

//******************************************************************************
//
// The following are defines for the offset address of the SIM_BASE
//
//******************************************************************************
#define SIM_O_SOPT1				0x00000000
#define SIM_O_SOPT2				0x00001004
#define SIM_O_SOPT4				0x0000100C
#define SIM_O_SOPT5				0x00001010
#define SIM_O_SOPT6				0x00001014
#define SIM_O_SOPT7				0x00001018
#define SIM_O_SDID				0x00001024
#define SIM_O_SCGC1				0x00001028
#define SIM_O_SCGC2				0x0000102C
#define	SIM_O_SCGC3				0x00001030
#define SIM_O_SCGC4				0x00001034
#define SIM_O_SCGC5				0x00001038
#define SIM_O_SCGC6				0x0000103C
#define SIM_O_SCGC7				0x00001040
#define SIM_O_CLKDIV1			0x00001044
#define SIM_O_CLKDIV2			0x00001048
#define SIM_O_FCFG1				0x0000104C
#define SIM_O_FCFG2				0x00001050
#define SIM_O_UIDH				0x00001054
#define SIM_O_UIDMH				0x00001058
#define SIM_O_UIDML				0x0000105C
#define SIM_O_UIDL				0x00001060

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT1 register.
//
//******************************************************************************
#define	SIM_SOPT1_RAMSIZE_MSK	0x0000F000	//RAM size
#define	SIM_SOPT1_RAM_32K		0x00005000	//32K RAM
#define SIM_SOPT1_RAM_64K		0x00007000	//64K RAM
#define SIM_SOPT1_RAM_96K		0x00008000	//96K RAM
#define SIM_SOPT1_RAM_128K		0x00009000	//128K RAM
#define SIM_SOPT1_OSC32KSEL		0x00080000	//32K oscillator clock select
#define SIM_SOPT1_MS			0x00800000	//EzPort chip select pin state
#define SIM_SOPT1_USBSTBY		0x40000000	//USB voltage regulator in standby mode
#define SIM_SOPT1_USBREGEN		0x80000000	//USB voltage regulator enable

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT2 register.
//
//******************************************************************************
#define SIM_SOPT2_MCGCLKSEL		0x00000001	//MCG clock select
#define	SIM_SOPT2_FBSL_MSK		0x00000300	//FlexBus security level
#define SIM_SOPT2_CMTUARTPAD	0x00000800	//CMT/UART pad drive strength
#define SIM_SOPT2_TRACECLKSEL	0x00001000	//Debug trace clock select
//#define	SIM_SOPT2_PLLFLLSEL		0x00010000	//PLL/FLL clock select
#define SIM_SOPT2_USBSRC		0x00040000	//USB clock source select
#define SIM_SOPT2_TIMESRC_MSK	0x00300000	//IEEE 1588 timestamp clock source select
#define SIM_SOPT2_I2SSRC_MSK	0x03000000	//I2S master clock source select
#define SIM_SOPT2_SDHCSRC_MSK	0x30000000	//SDHC clock source select

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT4 register.
//
//******************************************************************************
#define SIM_SOPT4_FTM0FLT0		0x00000001	//FTM0 Fault 0 Select
#define SIM_SOPT4_FTM0FLT1		0x00000002	//FTM0 Fault 1 Select
#define SIM_SOPT4_FTM0FLT2		0x00000004	//FTM0 Fault 2 Select
#define	SIM_SOPT4_FTM1FLT0		0x00000010	//FTM1 Fault 0 Select
#define SIM_SOPT4_FTM2FLT0		0x00000100	//FTM2 Fault 0 Select
#define SIM_SOPT4_FTM1CH0SRC_MSK	0x000C0000	//FTM1 channel 0 input capture source select
#define SIM_SOPT4_FTM2CH0SRC_MSK	0x00300000	//FTM2 channel 0 input capture source select
#define SIM_SOPT4_FTM0CLKSEL	0x01000000	//FlexTimer 0 External Clock Pin Select
#define SIM_SOPT4_FTM1CLKSEL	0x02000000	//FlexTimer 1 External Clock Pin Select
#define SIM_SOPT4_FTM2CLKSEL	0x04000000	//FlexTimer 2 External Clock Pin Select

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT5 register.
//
//******************************************************************************
#define SIM_SOPT5_UART0TXSRC_MSK	0x00000003	//UART 0 transmit data source select
#define SIM_SOPT5_UART0RXSRC_MSK	0x0000000C	//UART 0 receive data source select
#define SIM_SOPT5_UARTTXSRC_MSK		0x00000030	//UART 1 transmit data source select
#define SIM_SOPT5_UART1RXSRC_MSK	0x000000C0	//UART 1 receive data source select

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT6 register.
//
//******************************************************************************
#define SIM_SOPT6_RSTFLTSEL_MSK		0x1F000000	//Reset pin filter select
#define SIM_SOPT6_RSTFLTEN_MSK		0xE0000000	//Reset pin filter enable

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SOPT7 register.
//
//******************************************************************************
#define SIM_SOPT7_ADC0TRGSEL_MSK	0x0000000F	//ADC0 trigger select
#define SIM_SOPT7_ADC0PRETRGSEL		0x00000010	//ADC0 pretrigger select
#define SIM_SOPT7_ADC0ALTTRGEN		0x00000080	//ADC0 alternate trigger enable
#define SIM_SOPT7_ADC1TRGSEL_MSK	0x00000F00	//ADC1 trigger select
#define SIM_SOPT7_ADC1PRETRGSEL		0x00001000	//ADC1 pre-trigger select
#define SIM_SOPT7_ADC1ALTTRGEN		0x00008000	//ADC1 alternate trigger enable

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SDID register.
//
//******************************************************************************
#define SIM_SDID_PINID_MSK			0x0000000F	//Pincount identification
#define SIM_SDID_PIN_32				0x00000002	//32 Pin
#define SIM_SDID_PIN_48				0x00000004	//48 Pin
#define SIM_SDID_PIN_64				0x00000005	//64 Pin
#define SIM_SDID_PIN_80				0x00000006	//80 Pin
#define SIM_SDID_PIN_81				0x00000007	//81 Pin
#define SIM_SDID_PIN_100			0x00000008	//100 Pin
#define SIM_SDID_PIN_121			0x00000009	//121 Pin
#define SIM_SDID_PIN_144			0x0000000A	//144 Pin
#define SIM_SDID_PIN_196			0x0000000C	//196 Pin
#define SIM_SDID_PIN_256			0x0000000E	//256 Pin
#define SIM_SDID_FAMID_MSK			0x00000070	//Kinetis family identification
#define SIM_SDID_FAMID_K10			0x00000000	//K10
#define SIM_SDID_FAMID_K20			0x00000010	//K20
#define SIM_SDID_FAMID_K30			0x00000020	//K30
#define SIM_SDID_FAMID_K40			0x00000030	//K40
#define SIM_SDID_FAMID_K60			0x00000040	//K60
#define SIM_SDID_FAMID_K70			0x00000050	//K70
#define SIM_SDID_FAMID_K502			0x00000060	//K50 and K52
#define SIM_SDID_FAMID_K513			0x00000070	//K51 and K53
#define SIM_SDID_REVID_MSK			0x0000F000	//Device revision number

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC1 register.
//
//******************************************************************************
#define SIM_SCGC1_UART4				0x00000400	//UART4 Clock Gate Control
#define SIM_SCGC1_UART5				0x00000800	//UART5 Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC2 register.
//
//******************************************************************************
#define SIM_SCGC2_ENET				0x00000001	//ENET Clock Gate Control
#define SIM_SCGC2_DAC0				0x00001000	//DAC0 Clock Gate Control
#define SIM_SCGC2_DAC1				0x00002000	//DAC1 Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC3 register.
//
//******************************************************************************
#define SIM_SCGC3_RNGB				0x00000001	//RNGB Clock Gate Control
#define SIM_SCGC3_FLEXCAN1			0x00000010	//FlexCAN1 Clock Gate Control
#define SIM_SCGC3_SPI2				0x00001000	//SPI2 Clock Gate Control
#define SIM_SCGC3_SDHC				0x00020000	//SDHC Clock Gate Control
#define SIM_SCGC3_FTM2				0x01000000	//FTM2 Clock Gate Control
#define SIM_SCGC3_ADC1				0x08000000	//ADC1 Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC4 register.
//
//******************************************************************************
#define SIM_SCGC4_EWM				0x00000002	//EWM Clock Gate Control
#define SIM_SCGC4_CMT				0x00000004	//CMT Clock Gate Control
#define SIM_SCGC4_I2C0				0x00000040	//I2C0 Clock Gate Control
#define SIM_SCGC4_I2C1				0x00000080	//I2C1 Clock Gate Control
#define SIM_SCGC4_UART0				0x00000400	//UART0 Clock Gate Control
#define SIM_SCGC4_UART1				0x00000800	//UART1 Clock Gate Control
#define SIM_SCGC4_UART2				0x00001000	//UART2 Clock Gate Control
#define SIM_SCGC4_UART3				0x00002000	//UART3 Clock Gate Control
#define SIM_SCGC4_USBOTG			0x00040000	//USB Clock Gate Control
#define SIM_SCGC4_CMP				0x00080000	//Comparator Clock Gate Control
#define SIM_SCGC4_VREF				0x00100000	//VREF Clock Gate Control
#define SIM_SCGC4_LLWU				0x10000000	//LLWU Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC5 register.
//
//******************************************************************************
#define SIM_SCGC5_LPTIMER			0x00000001	//Low Power Timer Clock Gate Control
#define SIM_SCGC5_REGFILE			0x00000002	//Register File Clock Gate Control
#define SIM_SCGC5_TSI				0x00000020	//TSI Clock Gate Control
#define SIM_SCGC5_PORTA				0x00000200	//Port A Clock Gate Control
#define SIM_SCGC5_PORTB				0x00000400	//Port B Clock Gate Control
#define SIM_SCGC5_PORTC				0x00000800	//Port C Clock Gate Control
#define SIM_SCGC5_PORTD				0x00001000	//Port D Clock Gate Control
#define SIM_SCGC5_PORTE				0x00002000	//Port E Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC6 register.
//
//******************************************************************************
#define SIM_SCGC6_FTFL				0x00000001	//Flash Memory Clock Gate Control
#define SIM_SCGC6_DMAMUX			0x00000002	//DMA Mux Clock Gate Control
#define SIM_SCGC6_FLEXCAN0			0x00000010	//FlexCAN0 Clock Gate Control
#define SIM_SCGC6_SPI0				0x00001000	//SPI0 Clock Gate Control
#define SIM_SCGC6_SPI1				0x00002000	//SPI1 Clock Gate Control
#define SIM_SCGC6_I2S				0x00008000	//I2S Clock Gate Control
#define SIM_SCGC6_CRC				0x00040000	//CRC Clock Gate Control
#define SIM_SCGC6_USBDCD			0x00200000	//USB DCD Clock Gate Control
#define SIM_SCGC6_PDB				0x00400000	//PDB Clock Gate Control
#define SIM_SCGC6_PIT				0x00800000	//PIT Clock Gate Control
#define SIM_SCGC6_FTM0				0x01000000	//FTM0 Clock Gate Control
#define SIM_SCGC6_FTM1				0x02000000	//FTM1 Clock Gate Control
#define SIM_SCGC6_ADC0				0x08000000	//ADC0 Clock Gate Control
#define SIM_SCGC6_RTC				0x20000000	//RTC Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_SCGC7 register.
//
//******************************************************************************
#define SIM_SCGC7_FLEXBUS			0x00000001	//FlexBus Clock Gate Control
#define SIM_SCGC7_DMA				0x00000002	//DMA Clock Gate Control
#define SIM_SCGC7_MPU				0x00000004	//MPU Clock Gate Control

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_CLKDIV1 register.
//
//******************************************************************************
#define SIM_CLKDIV1_OUTDIV4_MSK		0x000F0000	//Clock 4 output divider value
#define SIM_CLKDIV1_OUTDIV3_MSK		0x00F00000	//Clock 3 output divider value
#define SIM_CLKDIV1_OUTDIV2_MSK		0x0F000000	//Clock 2 output divider value
#define SIM_CLKDIV1_OUTDIV1_MSK		0xF0000000	//Clock 1 output divider value

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_CLKDIV2 register.
//
//******************************************************************************
#define SIM_CLKDIV2_USBFRAC			0x00000001	//USB clock divider fraction
#define SIM_CLKDIV2_USBDIV_MSK		0x0000000E	//USB clock divider divisor
#define SIM_CLKDIV2_I2SFRAC_MSK		0x0000FF00	//I2S clock divider fraction
#define SIM_CLKDIV2_I2SDIV_MSK		0xFFF00000	//I2S clock divider value

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_FCFG1 register.
//
//******************************************************************************
#define SIM_FCFG1_DEPART_MSK		0x00000F00	//FlexNVM partition
#define SIM_FCFG1_EESIZE_MSK		0x000F0000	//EEPROM size
#define SIM_FCFG1_EESIZE_0B			0x000F0000	//0 Byte
#define SIM_FCFG1_EESIZE_32B		0x00090000	//32 Byte
#define SIM_FCFG1_EESIZE_64B		0x00080000	//64 Byte
#define SIM_FCFG1_EESIZE_128B		0x00070000	//128 Byte
#define SIM_FCFG1_EESIZE_256B		0x00060000	//256 Byte
#define SIM_FCFG1_EESIZE_512B		0x00050000	//512 Byte
#define SIM_FCFG1_EESIZE_1K			0x00040000	//1K Byte
#define SIM_FCFG1_EESIZE_2K			0x00030000	//2k Byte
#define SIM_FCFG1_EESIZE_4K			0x00020000	//4K Byte
#define SIM_FCFG1_PFSIZE_MSK		0x0F000000	//Program flash size
#define SIM_FCFG1_PFSIZE_128K		0x07000000	//128K Byte
#define SIM_FCFG1_PFSIZE_256K		0x09000000	//256K Byte
#define SIM_FCFG1_PFSIZE_512K		0x0B000000	//512K Byte
#define SIM_FCFG1_NVMSIZE_MSK		0xF0000000	//FlexNVM size
#define SIM_FCFG1_NVMSIZE_0K		0x00000000	//0 Byte
#define SIM_FCFG1_NVMSIZE_128K		0x70000000	//128 KB of FlexNVM, 16 KB protection region
#define SIM_FCFG1_NVMSIZE_256K		0x90000000	//256 KB of FlexNVM, 32 KB protection region
#define SIM_FCFG1_NVMSIZE_256k		0xF0000000	//256 KB of FlexNVM, 32 KB protection region

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_FCFG2 register.
//
//******************************************************************************
#define SIM_FCFG2_MAXADDR1_MSK		0x003F0000	//Max address block 1
#define SIM_FCFG2_PFLSH				0x00800000	//Program flash
#define SIM_FCFG2_MAXADDR0_MSK		0x3F000000	//Max address block 0
#define SIM_FCFG2_SWAPPFLSH			0x80000000	//Swap program flash

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_UIDH register.
//
//******************************************************************************
#define SIM_UIDH_MSK				0xFFFFFFFF	//UID,Unique Identification

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_UIDMH register.
//
//******************************************************************************
#define SIM_UIDMH_MSK				0xFFFFFFFF	//UID,Unique Identification

//******************************************************************************
//
// The following are defines for the bit fields in the SIM_UIDML register.
//
//******************************************************************************
#define SIM_UIDML_MSK				0xFFFFFFFF	//UID,Unique Identification


//******************************************************************************
//
// The following are defines for the bit fields in the SIM_UIDL register.
//
//******************************************************************************
#define SIM_UIDL_MSK				0xFFFFFFFF	//UID,Unique Identification

//******************************************************************************
//
// The following are defines for the Peripheral Clock Enable.
//
//******************************************************************************
#define	SIM_PERIPH_GPIOA			0x00091038
#define	SIM_PERIPH_GPIOB			0x000A1038
#define	SIM_PERIPH_GPIOC			0x000B1038
#define	SIM_PERIPH_GPIOD			0x000C1038
#define	SIM_PERIPH_GPIOE			0x000D1038
#define SIM_PERIPH_I2C0				0x00061034
#define SIM_PERIPH_I2C1				0x00071034
#define SIM_PERIPH_UART0			0x000A1034
#define SIM_PERIPH_UART1			0x000B1034
#define SIM_PERIPH_UART2			0x000C1034
#define SIM_PERIPH_UART3			0x000D1034
#define SIM_PERIPH_UART4			0x000A1028
#define SIM_PERIPH_UART5			0x000B1028
#define SIM_PERIPH_TSI				0x00051038
#define SIM_PERIPH_SPI0				0x000C103C
#define SIM_PERIPH_SPI1				0x000D103C
#define SIM_PERIPH_SPI2				0x000C1030
#define SIM_PERIPH_I2S				0x000F103C
#define SIM_PERIPH_FTM0				0x0018103C
#define SIM_PERIPH_FTM1				0x0019103C
#define SIM_PERIPH_FTM2				0x00181030
#define SIM_PERIPH_ENET				0x0000102C
#define SIM_PERIPH_DAC0				0x000C102C
#define SIM_PERIPH_DAC1				0x000d102C
#define SIM_PERIPH_ADC0				0x001B103C
#define SIM_PERIPH_ADC1				0x001B1030
#define SIM_PERIPH_RNGB				0x00001030
#define SIM_PERIPH_FLEXCAN0			0x0004103C
#define SIM_PERIPH_FLEXCAN1			0x00041030
#define SIM_PERIPH_SDHC				0x00111030
#define SIM_PERIPH_EWM				0x00011034
#define SIM_PERIPH_CMT				0x00021034
#define SIM_PERIPH_CMP				0x00131034
#define SIM_PERIPH_USBOTG			0x00121034
#define SIM_PERIPH_USBDCD			0x0015103C
#define SIM_PERIPH_VREF				0x00141034
#define SIM_PERIPH_LLWU				0x001C1034
#define SIM_PERIPH_LPTIMER			0x00001038
#define SIM_PERIPH_REGFILE			0x00011038
#define SIM_PERIPH_FTFL				0x0000103C
#define SIM_PERIPH_DMAMUX			0x0001103C
#define SIM_PERIPH_CRC				0x0012103C
#define SIM_PERIPH_PDB				0x0016103C
#define SIM_PERIPH_PIT				0x0017103C
#define SIM_PERIPH_RTC				0x001D103C
#define SIM_PERIPH_FLEXBUS			0x00001040
#define SIM_PERIPH_DMA				0x00011040
#define SIM_PERIPH_MPU				0x00021040

//******************************************************************************
//
// The following are defines for the Peripheral Clock Source Select.
//
//******************************************************************************
#define	SIM_SRC_OSC32K				0x00130000
#define	OSC32K_SYS					0x00		//System oscillator(OSC32KCLK)
#define	OSC32K_RTC					0x01		//RTC oscillator
#define	SIM_SRC_SDHC				0x001C1004
#define	SDHC_SYS					0x00		//Core/System clock
#define	SDHC_MCG					0x01		//MCGPLLCLK/MCGFLLCLK Clock
#define	SDHC_OSC					0x02		//OSCERCLK clock
#define	SDHC_EXT					0x03		//External bypass clock(SDHC0_CLKIN)
#define	SIM_SRC_I2S					0x00181004
#define	I2S_SYS						0x00		//Core/system clock divided by the I2S fractional clock divider.
#define	I2S_MCG						0x01		//MCGPLLCLK/MCGFLLCLK clock divided by the I2S fractional clock divider.
#define	I2S_OSC						0x02		//OSCERCLK clock
#define	I2S_EXT						0x03		//External bypass clock (I2S0_CLKIN)
#define	SIM_SRC_TIMESTAMP			0x00141004
#define	TIMER_SYS					0x00		//Core/system clock.
#define	TIMER_MCG					0x01		//MCGPLLCLK/MCGFLLCLK clock
#define	TIMER_OSC					0x02		//OSCERCLK clock
#define	TIMER_EXT					0x03		//External bypass clock (ENET_1588_CLKIN).
#define	SIM_SRC_USB					0x00121004
#define	USB_EXT						0x00		//External bypass clock (USB_CLKIN).
#define	USB_MCG						0x01		//MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider.
#define	SIM_SRC_PLLFLL				0x00101004
#define	PLLFLL_FLL					0x00		//MCGFLLCLK clock
#define	PLLFLL_PLL					0x01		//MCGPLLCLK clock
#define	SIM_SRC_TRACE				0x000C1004
#define	TRACE_MCG					0x00		//MCGOUTCLK
#define	TRACE_SYS					0x01		//Core/system clock
#define	SIM_SRC_MCG					0x00001004
#define	MCG_SYS						0x00		//System oscillator (OSCCLK)
#define	MCG_RTC						0x01		//32 kHz RTC oscillator


//******************************************************************************
//
// The following are defines for the RAM Size.
//
//******************************************************************************
#define	SIM_RAM_32K					0x00005000	//32K RAM
#define SIM_RAM_64K					0x00007000	//64K RAM
#define SIM_RAM_96K					0x00008000	//96K RAM
#define SIM_RAM_128K				0x00009000	//128K RAM

//******************************************************************************
//
// The following are defines for the Family.
//
//******************************************************************************
#define SIM_FAMID_K10				0x00000000	//K10
#define SIM_FAMID_K20				0x00000010	//K20
#define SIM_FAMID_K30				0x00000020	//K30
#define SIM_FAMID_K40				0x00000030	//K40
#define SIM_FAMID_K60				0x00000040	//K60
#define SIM_FAMID_K70				0x00000050	//K70
#define SIM_FAMID_K502				0x00000060	//K50 and K52
#define SIM_FAMID_K513				0x00000070	//K51 and K53

//******************************************************************************
//
// The following are defines for the Pin Number.
//
//******************************************************************************
#define SIM_PIN_32					0x00000002	//32 Pin
#define SIM_PIN_48					0x00000004	//48 Pin
#define SIM_PIN_64					0x00000005	//64 Pin
#define SIM_PIN_80					0x00000006	//80 Pin
#define SIM_PIN_81					0x00000007	//81 Pin
#define SIM_PIN_100					0x00000008	//100 Pin
#define SIM_PIN_121					0x00000009	//121 Pin
#define SIM_PIN_144					0x0000000A	//144 Pin
#define SIM_PIN_196					0x0000000C	//196 Pin
#define SIM_PIN_256					0x0000000E	//256 Pin

extern void SIMPeripheralEnable(unsigned long ulPeripheral);
extern unsigned long SIMGetRamSize(void);
extern unsigned long SIMGetRevID(void);
#endif//__SIM_H__

